1. Field of the Invention
The present invention relates to a counter circuit, and, more particularly relates to a counter circuit that can suitably count a clock signal in which hazard easily occurs. Furthermore, the present invention relates to a latency counter, and, more particularly relates to a latency counter that counts a latency of an internal command within a synchronous memory. Further, the present invention relates to a semiconductor memory device including such a latency counter and also relates to a data processing system including such a semiconductor memory device.
2. Description of Related Art
Synchronous memories represented by a synchronous DRAM (Synchronous Dynamic Random Access Memory) are widely used as a main memory or the like of personal computers. In the synchronous memory, data is inputted and outputted in synchronism with a clock signal supplied from a controller. Thus, when a higher-speed clock is used, the data transfer rate can be increased.
However, because a DRAM core is consistently operated by an analog operation also in the synchronous DRAM, a considerably weak charge needs to be amplified by a sensing operation. Accordingly, it is not possible to shorten the time from issuing a read command to outputting first data. After the elapse of a predetermined delay time from the read command is issued, the first data is outputted in synchronism with an external clock.
This delay time is generally called “CAS latency” and is set to an integral multiple of a clock cycle. For example, when the CAS latency is 5 (CL=5), the read command is fetched in synchronism with the external clock, and thereafter, the first data is outputted in synchronism with the external clock that is after five cycles. That is, the first data is outputted after the elapse of the five clocks. A counter that counts such latency is called “latency counter”.
As the latency counter, a circuit described in Japanese Patent Application Laid-open (JP-A) No. 2008-47267 proposed by the present inventor(s) is well known. The latency counter described in JP-A No. 2008-47267 includes a ripple counter that outputs a count value in a binary format and a point-shift FIFO circuit, in which by a count value of the ripple counter, an input gate and an output gate of the point-shift FIFO circuit are controlled. The reason for using the ripple counter as the counter circuit is due to a consideration of a point that hazard easily occurs in a clock signal that should be counted.
Japanese Patent Application Laid-open No. 2007-115351 discloses a similar circuit, as another patent document related to the latency counter.
As described above, it is difficult to shorten a time from the read command is issued until the first data is outputted. Thus, when the frequency of the clock signal becomes higher, the latency inevitably increases. Thus, when the frequency of the clock signal becomes higher, a count of a larger latency is required for the latency counter. To count the larger latency, it suffices that the number of latch circuits configuring the point-shift FIFO circuit is increased.
However, in the latency counter described in Japanese Patent Application Laid-open No. 2008-47267, outputs of all the latch circuits configuring the point-shift FIFO circuit are wired-OR connected. Thus, in proportion to the number of latch circuits, an output load becomes larger. Thus, there is a problem that when the number of latch circuits increases, the waveform of the outputted internal command becomes dull, thereby deteriorating a signal quality.